M-Vision 1000

Interrupt Handler

One of the key features of the MV-1000 hardware and software is the availability to the user of an interrupt handler. A hardware interrupt tells the processor that it must do something. When the MV-1000 is put into "master mode" the user can enable a hardware interrupt at the "end of frame" or the "end of transfer". There are two bits on the MV-1000 that allow the processor to determine which interrupt has occured.

The processor is completely unburdened from any overhead with the transfer save servicing one or two interrupts per "frame", with line scan cameras, we set up a pseudo frame. The processor can work the entire time on the data in system memory. The MV-1000 manages the entire transfer transaction without the intervention of the CPU. The PCI bridge arbitrates the access to the memory, so there is no conflict. There is sample source code delivered with all SDKs that set up two buffers on the MV-1000 and set up two buffers in the system memory. The interrupt for "end of transfer" assures that the data in system memory is valid.

Typical applications:

	The MV-1000 can be set up with a hardware trigger. The board will automatically grab the image when triggered and transfer it to system memory and give the processor an interupt telling it that the transfer is complete. This will occur at every trigger. The processor can work the entire time on the data in system memory.
	Line Scan: Two buffers can be set up on the MV-1000 and two in system memory. Data will be continuously tansferred to the two buffers in system memory in a ping pong fashion. The processor can implement inspection algorithms on the data in system memory without being burdened by the processor. You get all the data free from overhead on the processor.
	Hughes uses the MV1000 with the MV1300 to have 6 Pulnix TM9701 analog cameras hooked up. They trigger the board, and the MV1000 takes images of the cameras sequentially and stores the images to system memory.

With some other frame grabbers, the user needs to poll a bit on the board to determine when the transfer is complete and data valid, tying up the processor. The processor has the highest priority on the bus. If you need to poll a bit on the board, the transfer speed will be significantly impacted. Some boards generate one or more interrupts per line tying up the processor during transfer. Others don't have the interrupt available to the user, so the processor has to wait until the program returns, or it needs to continuously poll a bit on the board. Without a "transfer complete" interrupt, determining when data is valid in system memory becomes an issue in time critical applications.


MuTech Corp. July 1996
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