MV1000 Application Notes

	MCLK (RS-422): Master Clock is used as the main clock. Some models do not need the MCLK signal, because it is generated by an internal crystal. Some models use crystal when there is no MCLK input, but lock to the MCLK signal when it is present. Check with Dalsa Customer Support for your specific model. Also if the model is using crystal, find out the exact frequency.
	EXSYNC (RS-422, Active High): All Dalsa LS cameras require this signal. It determins the scan line. The duration of the pulse must be greater than 100 ns. No maximum duration is specified from Dalsa, but a few MCLK clock periods have been tested successfully. The minimum period of EXSYNC is specified as the number of pixels per line plus a fixed number M (usually 30 to 50 depending on the camera model, and this can be found in the camera manual) of PIXCLK periods. For the relationship between PIXCLK and MCLK, please refer to next section. There is no specification for maximum period, longer periods worked well, please see the Exposure Control Section for the pros and cons of a long line period.
	PRIN (RS-422, Active Low): Exposure Reduction Control Signal is an optional signal. When it is low, the CCD sensor is discharging, i.e. no exposure. When PRIN goes high, the CCD sensor cells start charging. A static high PRIN means the exposure time is the whole line. When there is a low duration within a line, the actual exposure time is between the rising edge and the end of the line (EXSYNC going high). Dalsa manual says the falling edge of PRIN must be after the rising edge of LVAL (described later).
	BINNING Control (RS-422, Active High): This is a static control signal. It controls the BINNING feature of the camera. When the BINNING is ON, two adjacent pixels are combined together and sent out as one pixel (how the combination is done is not described), so a 2048 pixel/line camera outputs only 1024 pixels in a line. The BINNING is not supported by all LS cameras, so check with your Dalsa customer support to determine if your model has that feature. The BINNING control is not supported by MV-1100, since it is a static signal, the user can always wire the cable connector to control it.

	PVAL/STROBE (RS-422): This is the clock output from the camera for strobbing in the pixel data. Dalsa digital camera usually have the PVAL on the DB-25 connector and the STROBE on the CID-20 connector. They are basically the same signal with different skews. For most of the Dalsa LS cameras, the falling edges of PVAL/STROBE are used. If your specific camera requires using the falling edges, see later section for correct settings. Dalsa camera manual suggests using the STROBE instead of the PVAL because it is better aligned with the data. The MVCDLS cable connects the STROBE signal to the Pixel Clock Input of the MV-1100
	LVAL (RS-422): This is the line data valid signal from the camera. Almost all Dalsa cameras use active high on this signal. The LVAL becomes high, X pixel clocks after the EXSYNC (input) is over. Then, the first valid pixel data is presented on the data lines Y pixel clocks after the LVAL becoming high. The specific value for X and Y must be found in the manual of the camera.
	CCLK (RS-422): This output is the MCLK input signal delayed by a certain time inside the camera. The camera sends it out after a certain latancy delay, in case some frame grabber require it. MV-1100 is not using this signal. On the MVCDLS cable, CCLK is not connected to the MV-1100.

	The EXSYNC signal must be present, must have the correct polarity, and the minimum period of the EXSYNC must satisfy the one described above (in EXSYNC section);
	The PRIN signal must NOT be low statically, must be synchronized with the EXSYNC, and the falling edge must happen after the LVAL goes high;
	If your camera model requires the MCLK (you must check with Dalsa for the model), then the MCLK signal must be present, and must be equal to or less than the specified MCLK frequency.

	Flag_Digital_Cam: must be 1 for digital camera;
	Flag_Line_Scan: must be 1, otherwise will not work with LS camera;
	Tim_Gen_Enable: must be 1, if you need to send the MCLK to drive the camera;
	Data_Packing: set to 1 for 8 bit monochrome LS camera, set to 4 for color LS camera;

Clock_Reference_Select: must be 3, using on board 14.3MHz crystal as the reference of the PLL, the PLL then generates the required MCLK/PCLK frequency based on next entry;

Pixel_Clock_Freq: set to desired frequency (float). If your camera requires the Master Clock, the desired frequency could be the same (or twice, or quardraple) as the pixel clock frequency (find out from your Dalsa camera manual). If your camera DOES NOT require the Master Clock, it will ignore the MCLK signal sent, then this entry can be set rather freely as long as this frequency and the Camera_Pixel_Per_Line in [TimGen Control] section result in an EXSYNC signal which satisfies the requirement given in the 1st section of this App. Note;

	Camera_Drive_HPolarity: must be set according to the EXSYNC specification. If the EXSYNC is active high, set this to 1 (the H. Drive is passed as EXSYNC by MV-1100);
	Camera_Master_Clock: should be set to 0 for normal use;
	Camera_Pixel_Per_Line: must be set according to the H. resolution of the LS camera. This entry controls the number of Timing Generator Clock cycles/line, i.e. the H. Drive period (EXSYNC period) in terms of Timing Generator Clock cycles. Note, the Timing Generator Clock frequency is equal to the MCLK frequency (controlled by Pixel_Clock_Freq entry in the [PLL Control] section), if the Tim_Gen_Clock_D4 (described below) is set to 0. If the Tim_Gen_Clock_D4 is set to 1 (the PLL clock is divided by 4 before being sent to the Timing Generator), then the Timing Generator Clock frequency is one forth of the MCLK frequency. Also note that when the "D4" is enabled, only the clock of Timing Generator is divided, the MCLK signal frequency is still equal to the PLL clock frequency. You must satify the EXSYNC signal timing requirement of your LS camera by specifying the Pixel_Clock_Freq, the Tim_Gen_Clock_D4 and this entry.
	Tim_Gen_Clock_D4: set to 1 to divide the PLL clock by 4 before it is used by Timing Generator, set to 0 for NO division. Note, the MCLK signal is always equal to the PLL clock (without division). The reason we need to divide the PLL clock by 4 is explained below. All registers in Timing Generator are 12 bit wide, the maximum value can be loaded without overflow is 4095. For those Dalsa camera which require the MCLK frequency being twice that of the PCLK frequency, the maximum H. resolution for which the EXSYNC signal requirement can be satisfied is 1024. For 2048 (or higher) line scan cameras, if the M (see Section 1-a for the meaning of M) specified by Dalsa is 40, then we need at least 4096+40 MCLK cycles (PLL cycles) per line to satisfy this requirement. And this overflows the Timing Generator register. If we divide the PLL frequency by 4 then use it as the Timing Generator clock, then the TimGen clock per line required becomes 1024+10=1034, this is well below the overflow value. Using the same reasoning, we can have the rule of thumb for setting the Tim_Gen_Clock_D4 as: if your camera requires MCLK = 2 * PCLK and its resolution is 2048 or higher, then set it to 1; if your camera uses MCLK = PCLK and its resolution is 4096 or higher, then set it to 1; otherwise set it to 0.

	Flag_LS_Exp_En: used to enable the Line Scan Exposure Reduction (PRIN) signal. Normally, we suggest it is enabled (set to 1) at all time, the user can disable the PRIN by changing next entry LS_Exp_Start.
	LS_Exp_Start: specifies the starting position of the PRIN signal (falling edge, the PRIN is always active LOW). Since this is implemented in Timing Generator, the unit of value is the same as Camera_Pixel_Per_Line. Using 0 or 1 for this entry will cause PRIN signal to be high all the time (even if the Flag_LS_Exp_En is set to1), it can be used as an enable/disable too. Dalsa LS cameras require that the PRIN does not go LOW until the LVAL signal goes HIGH. To satisfy that, we suggest to set LS_Exp_Start to 10 and to set Camera_Drive_Width, in [Timing Generator Control] section, to 4.
	LS_Exp_End: specifies the ending position of the PRIN signal. Once the Flag_LS_Exp_En and the LS_Exp_Start entries are set, this is the control of the exposure time (between the rising edge of PRIN and the beginning of the next EXSYNC), the larger this value the less exposion.

	Flag_LDV_Inv: should be set to 0, most of the time, for Dalsa LS camera;
	Flag_PCLK_Inv: should be set to 1, most of the time.

C:>>camtest lsconf.ini

C:>>rgblscan lsconf.ini

	Run the diagnostic software (MV1DIAG), making sure that MV-1000 and MV-1100 are on working order;
	If possible, connecting a RS170/CCIR standard analog camera to make sure that the MV-1000 board is grabbing fine;
	Double check the base board jumpers are set according to the MV-1100 Manual to accomondate the MV-1100 Module;
	Double check the MV-1100 jumpers are set according to this App. Note to work with line scan cameras.

	If your Dalsa camera requires the MCLK signal, or the camera can use either the internal or the external clock but you decided using the external MCLK, then check that the PCLK of the camera is locked to the MCLK. Connecting the CH 1 of the scope to JPD12 pin 2 (All 25 JPDs are located in the center-left part of the MV-1100 module, the top is JPD1, the bottom is PJD25, the pin 1 of JPDs are marked by square pads) of the MV-1100 module, and trigger on it, this is Pixel Clock (PCLK or PVAL) from the camera. Connecting the CH 2 of the scope to JPD12 pin 1, this is the Master Clock (MCLK) being sent to the camera. Now, check the following two points: (1) the PCLK is locked to the MCLK. If these two signals are free running with each other, then there is some thing wrong at either the MV-1100, the cable, or the camera. If there is no PCLK, check the cable or the camera output. If there is no MCLK, check the MV-1000 base board PLL section. (2) The PCLK period should be either one, two, or four (depending on your perticular camera) times of the MCLK period. If the division is wrong, recheck the camera manual or call Dalsa support to straight it out (it is important to know exactly the relation between these two signals).
	Checking the camera line rate is locked to the board EXSYNC signal by connecting the CH1 of the scope to JPD5 pin 1, and the CH2 probe to JPD5 pin 2. On CH1, you should see the EXSYNC signal with narraw duration (Note, the polarity is active high if you set the Flag_LDV_Inv of the [Digital Grab Control] section in the config. file to be 0, otherwise the polarity will be low). On CH2, you should see the LVAL signal, the high portion indecates the valid pixels and the rising edge should follow the EXSYNC with a small delay. (1) If they are not locked, check the cable and the camera; (2) If the EXSYNC is missing, check the MV-1000 Timing Generator section; (3) If the LVAL is missing, check the cable as well as the camera.
	Then checking the PRIN signal by moving the CH1 probe to pin 1 of JPD25. The following must be true: (1) The PRIN is statically LOW, a high is acceptible; (2) If there is signal, then the falling edge must following the LVAL rising edge with a small delay (the amount of the delay is not important).

	If the falling edge of the PCLK marks the stable duration of the data lines (most of the Dalsa LS cameras work this way, you can find out this information from the camera manual or by experimenting), the two jumpers should be set to FJ2 = Bottom, FJ3 = Left (see Case 1 above).
	If the rising edge of the PCLK is used by the camera, the jumpers should be set to FJ2 = Top, FJ3 = Right (see Case 2 above).
	If you can not find the timing relationship between the PCLK and the data, you can always try both ways and select the better one.

	Modifying the Pix_Clk_Freq entry in the [PLL Control] section of the config. file changes the line rate. Since the EXSYNC is generated by counting the Timing Generator Clock, reducing the PLL clock frequency reduces the line scan rate, and this squeezes the video vertically. The adjusting range of this method is limited by the MCLK locking range of the camera used, for those requiring the master clock input.
	The other method is modifying the Camera_Pixel_Per_Line entry in the [Timing Generator Control] section. This changes the period of EXSYNC signal without changing the pixel clock frequency. Increasing this value reduces the line rate and squeezes the video vertically. The lower limit of this is that the value can NOT be smaller than the H. resolution + M (see section 1-a and 3-c). The higher limit is that the register is 12 bit, any value bigger than 4095 will cause overflow (also see section 3-c for description of D4).
	The user can use one or both of the above methods to get the desired aspect ratio. But keep in mind that when the line period changes so is the exposure time. You can use the PRIN signal and the procedure described next to control the exposure.

	Starting with no exposure reduction (PRIN is statically high), by setting Flag_LS_Exp_En = 1, LS_Exp_Start = 0, and LS_Exp_End = 10. Then apply the light such that the video is brighter then you needed.
	Second, change the LS_Exp_End value to about half of Camera_Pixel_Per_Line, and change the LS_Exp_Start to about 10. This should significantely reduce the brightness of the video, which means the reduction is working. If no reduction is seen, increasing or decreasing the Start value such that the condition for PRIN signal (described in section 1- a and 3 - c) is satistied.
	Now, adjusting the LS_Exp_End value such that the desired exposure amount is reached.
	Note, that the adjustment of exposure can be easily done by changing the light or the aperture of the lense. So use those means first, and use PRIN only as the last step or fine tuning.

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