________________________________________________________________________
Application Note: MV-1000-019
Revision 1.0

Configuration files for custom camera interface to the MV-1000/MV-1100/MV-1300/MV-1350
____________________________________________________
Overview
M-Vision-1000
The M-Vision-1000 (MV-1000) is a monochrome digitizer board, which interfaces to the PCI bus. The MV-1000 product line includes the MV-1000 base board with analog camera support, a 3 Megabyte memory upgrade module (MV-1200), a digital camera interface module (MV-1100), an RGB module (MV-1300) and an NTSC/PAL, S-Video (Y/C) module (MV-1350).
To support a wide variety of cameras from line scan to area scan, interlaced or progressive scan video, free running or computer controlled; using different control schemes and different timing requirements, the MV-1000 family relies on camera configuration files to define the custom environment for proper operation of each camera.
Configuration Files
The configuration files are normally located in a sub-directory named CAMCFG in the MV-1000 base directory. They may be moved elsewhere for convenience.
Within this application note, different sections of the configuration file are discussed with explanations of the different parameters, when you need to change them, and how to determine the proper values. Because the text from the configuration file is intermixed with the discussion, the text from the configuration file appears in Courier font, while the normal text is Times New Roman.
Considerations when editing configuration files:
;!!!!! DOES NOT ALLOW EMPTY LINES BETWEEN ENTRIES IN EACH SECTION !!!!!!!
; This is an example of a comment. This line is disregarded.
H_Offset=0 100 ; Here 0 will be used, but 100 was once tried.
H_Offset=0x100 100 ; 256 is the current value, not 100 decimal.
[Miscellaneous]
The Contents of the Configuration File
[Miscellaneous]
This section is usually the first and is mostly for reference.
Version=2.1 ; Version of this camera configuration file
The version is 2.1. All discussions in this application note assume version 2.1. Certain older installations may use version 2.0 or 1.0, but it is recommended that they be updated to version 2.1. Note that this is the version of the configuration file format, not of the specific camera configuration file.
Camera_ID=MPES1.0
This is just the name of the camera for which this configuration file was created.
[General Control]
This section describes some general characteristics of the camera and the configuration.
Flag_Digital_Cam=1 ; 1 = digital camera, 0 = analog camera
This field indicates whether or not this camera uses the MV-1100, MV-1300, or MV-1350. An alternate meaning would be: Are you using a daughter board? 0=no, 1=yes
Flag_Line_Scan=0 ; 1 = Line scan camera, 0= Frame scan
This field indicates whether this camera is an area scan (0), or a line scan (1). Certain frame description signals and values are not meaningful for line scan cameras. However, lines from a line scan are usually accumulated to form a synthetic "Frame."
Tim_Gen_Enable=0 ; 1 = Enable timing generator
This field indicates whether or not this camera needs the Timing Generator circuitry on the MV-1000 to either drive the camera or for special internal timing.
Flag_Interlace=0 ; 1 = interlace video.
This field indicates whether this camera is interlaced (odd/even field=1) or progressive scan (0).
Pixel_Mode=0 ; 0 = 8 bits per pixel
; 1 = 10 bits per pixel
; 3 = 12 bits per pixel
; 4 = 16 bits per pixel
; 5 = 32 bits per pixel
; 6 = 16 bit YUV 4:2:2 per pixel
This field defines the size of each pixel. It is used in configuration files Version=2.1 or higher. Earlier versions of the configuration files use the following parameter.
Data_Packing=1 ; 1 = One byte/pixel
; 2 = Two bytes/pixel (10, 12, 16 bit)
; 4 = Four bytes/pixel (more than 16 bits)
This parameter is used in configuration files Version=2.0 or before. Any camera using 8 or less bits per pixel uses a 1 for this field. Cameras using 9-16 bits per pixel use a 2 in this field. Cameras using more than 16 bits per pixel use a 4 in this field. A special exception to this guideline is that when cameras interface to the MV-1300 version A2 or before, they may need to use 32 bits per pixel, even if they only use one or two color inputs at eight bits per color. However, if only the green channel is used on the MV-1300, this field may be 1 (for one byte/pixel).
[Ana. Video Selection]
This section deals with the MV-1000 base board only.
Video_Channel=0 ; Ranges from 0 to 3
This field controls the channel that will be specified by this configuration file. On the MVC-7 cable Red cable is 0, Green is 1, Blue is 2, and Gray is 3 (jumpers may be required and may change some channel assignments).
Flag_2Bit_Shiftdown=0 ; 0=normal 8 or 10 bit video
For 8-bit MV-1000 boards, this field is irrelevant. For 10-bit boards, a 0 means that all ten bits are used. A 1 in this field causes the incoming signal to be converted to 10 bit values, then shifted right to create an 8-bit value.
[Ana. Video Conditioning]
This section deals with the MV-1000 base board.
Filter_Cutoff=10 ; A frequency in Megahertz between 5 and 20.
This field controls the -3 dB cutoff frequency of a programmable filter on the MV-1000. The value specified should be an integer between 5 and 20. The filter can be bypassed via a jumper (JP5).
Filter_Boost=0 ; Boost value 0 to 3.
The Filter_Boost default is 0, which means no boost at high frequencies. Other values increase the boost.
AD_Convert_Top=0x66 ; Maximum voltage of incoming video.
This field controls the voltage of an 8-bit D/A converter used to specify the full-scale voltage of the incoming video signal. This value can range between 0 (0 Volts) and 255 (5 Volts). As the value decreases, any video signal above this threshold voltage is clipped at full-scale saturation. However, lower signal levels have finer effective resolution.
AD_Convert_Bottom=0x1f ; Minimum voltage of incoming video.
This field controls the voltage of an 8-bit D/A converter used to specify the low level (zero), offset voltage of the incoming video signal. This value can range between 0 (0 Volts) and 255 (5 Volts). As the value increases, any video signal below this threshold voltage is clipped at zero. However, higher signal levels have finer effective resolution.
Clamp_Level=0x3d ; Clamp Voltage
If Clamp_Control (see below) is at 1 or 2, this field controls the clamp voltage.
Clamp_Control=1 ; 0= No clamping, 1=Clamp at Back Porch, 2=Clamp at Sync. Tip.
This field defines where the clamping is to be applied.
DC_Offset=0x0 ; DC Offset voltage control
For DC coupled video, this controls the offset voltage which is subtracted from the video input. (Note, a bigger value in this entry causes the video to be more negative.) When Clamp_Control is 0, this field is used. JP6 must be IN to attach the DC Offset DAC.
[Sync/Trigger Selection]
This section controls synchronization characteristics for the MV-1000 base board. It also controls the video capture trigger, which may be used with daughter boards.
Sync_Channel=3 ; 0 = Gray line (on MVC-7 cable)
; 1 = Black line (on MVC-7 cable)
; 2 = Green line (on MVC-7 cable)
; 3 = Currently selected video line
Selects the Sync. source.
External_Sync_Input=0 ; 0 = Sync is stripped off Composite Video
; 1 = Separate Sync input used
When the incoming video contains the sync, select 0. If video and sync are separate, use 1.
External_CSync_Input=0 ; 1 = Separate C. Sync input used
; 0 = Separate H + V Sync input used
When External_Sync_Input (see above) is set to 1, this field defines whether the H and V sync are combined (0) or separate (1).
HSync_Polarity=0 ; Must be 0
This field must be 0, which means active low.
VSync_Trigger_Polarity=0 ; 0 = Active low.
; 1 = Active high.
For version 2.0, this controls the polarity of either vertical sync or capture trigger, determined by the value of External_Trigger as described below. When External_Trigger=0, VSync_Trigger_Polarity controls the Vsync polarity. When External_Trigger=1, VSync_Trigger_Polarity controls the trigger polarity.
VSync_Polarity=0 ; 0 = Active low.
; 1 = Active high.
For version 2.1, this controls the polarity of vertical sync.
Trigger_Polarity=0 ; 0 = Active low or falling edge.
; 1 = Active high or rising edge.
For version 2.1, this controls the polarity of the capture trigger. While MV-1000 is in continuous capture, the capture trigger is level sensitive. When MV-1000 is in single capture, the capture trigger is edge activated.
External_Trigger=0 ; 0 = No capture trigger.
; 1 = Use external trigger.
Enables the capture trigger for MV-1000 and all daughter boards. The capture trigger is connected to Yellow cable on MVC-7 when connected to MV-1000 version C7 or later. The Black cable is used on MV-1000 version C6 or earlier. Jumper JP25 must be in DOWN to connect the capture trigger to Yellow cable.
External_Clock=0 ; 0 = Use PLL clock.
; 1 = Use external clock.
This applies only to MV-1000 base board. If an external pixel clock is connected to Blue cable of MVC-7 and JP18 is IN, the external pixel clock will bypass the internal PLL.
Use_Module_Sync_Clock=0 ; 0 = Pixel clock timing from MV-1000
; 1 = Pixel clock timing from daughter board
When the pixel clock timing is received via an MV-1100 and the MV-1000 is used to digitize analog video, this entry selects the pixel clock on the MV-1100 instead of the PLL on the MV-1000.
[PLL Control]
This section defines the parameters for the Phase Locked Loop on the MV-1000.
H_Period=63.556000 ; The horizontal period (in microseconds)
This parameter specifies the horizontal period so that the correct PLL time range will be used. It is used when Clock_Reference_Select is 0 or 1.
Pixel_Per_Line=0x4f8 ; Number of pixel clock ticks per line
This is the pixel clock count per horizontal line. It specifies the number of pixel clock ticks in the entire horizontal line, not just the active video portion. This should be greater than the horizontal capture size. It is used when Clock_Reference_Select is 0 or 1.
Clock_Reference_Select=3 ; 0 = Stripped H. Sync.
; 1 = External H. Sync.
; 2 = External P. Clock.
; 3 = 14.3 MHz internal crystal.
This defines how the fundamental pixel timing will be generated. Different values lead to different parameters in this section being used.
Phase_Trimming=0x0 ; adjust the PLL clock phase
This will normally not be used. It adjusts the clock phase.
Pixel_Clock_Freq=20.000000 ; Frequency of pixel clock in MHz.
This is used when Clock_Reference_Select is 3. It specifies the clock frequency in MHz. The on-board 14.3 MHz crystal is used as a reference. The frequency may range to 40 MHz. It should be a floating point number.
Lead_Lag=0 ; 0 = Feedback lag reference
; 1 = Feedback lead reference
This will normally not be used.
Force_EQ_Remove=0 ; 0 = equalization is not removed in noninterlaced
; 1 = equalization is removed in noninterlaced
Equalization pulses are added in some sync signals. They are at half the normal horizontal period. If they are not removed, the PLL will increase the pixel clock rate to try to compensate for the shorter line length. They are assumed to be present in interlaced video, but not in noninterlaced video. Setting this field forces them to be removed in noninterlaced video.
[Grab Window Control]
This is the most often adjusted section. It controls the position of the grab window relative to the horizontal and vertical syncs.
H_Offset=0x0 ; number of pixels from the edge of horizontal sync
This parameter defines where the capture starts on each line. Depending on several factors, there may be a mandatory minimum.
V_Offset=0x1 ; number of lines, from the edge of vertical sync
This parameter defines where the capture starts on each frame or field. For interlaced video, this specifies the line number in each field where the capture starts.
H_Max_Capture_Size=640 ; Maximum number of pixels to capture per line
This parameter specifies the number of pixels per line. This value plus the H_Offset may not exceed the total pixel clock periods in the line.
V_Max_Capture_Size=480 ; Maximum number of lines to capture per frame
This parameter specifies the number of lines per frame. For interlaced video, it specifies the lines in a frame, not a field. Also, for interlaced video, this value divided by 2 plus the V_Offset may not exceed the total lines in the field. For non-interlaced video, this value plus the V_Offset may not exceed the total horizontal periods in the frame.
[Timing Generator Control]
This section is enabled when the Tim_Gen_Enable parameter in the [General Control] section is set to 1. It may be used to generate timing signals to drive cameras or it may be used as a source for the [Digital Camera Control] section below. The pixel clock, either generated by the PLL or taken from the external clock input, is used as the basis for this section.
Camera_CSync_Output=0 ; 0 = Driving with H. and V. Sync.
; 1 = Driving with C. Sync.
For composite sync, use 1. When 0 is used, separate horizontal and vertical syncs are generated.
Camera_Drive_VPolarity=1 ; 0 = drive C./V. Sync active low.
; 1 = drive C./V. Sync active high.
This field defines the polarity of vertical or composite sync depending on the value of Camera_CSync_Output defined above.
Camera_Drive_HPolarity=0 ; 0 = drive H. Sync active low.
; 1 = drive H. Sync active high.
This field defines the polarity of horizontal sync
Camera_Master_Clock=0 ; 0 = Not Master Clock, 1 = Master Clock
This should always be set to 0.
Camera_Pixel_Per_Line=0x3e8 ; number of pixel per line.
This field determines the period of the horizontal line. The unit is a clock tick. On the MV-1100 this may be used to define the period of EXSYNC.
Camera_Drive_Width=0x60 ; H. Drive Width, in number of pixels.
This field controls the width of the HSync pulse in clock ticks.
Camera_Drive_Height=0x3 ; V. Drive Height, in number of lines.
This field defines the width of the VSync pulse as a count of horizontal lines.
Camera_Line_Per_Frame=0x1f4 ; number of line in one frame.
This field determines the period of the frame (not a field, if interlaced timing is used). The unit is lines. For area scan cameras, this may be used to define the period of the EXSYNC signal.
Camera_Interlace=0 ; 0 = Noninterlaced, 1 = Interlaced
For driving interlaced cameras, this must be 1. Noninterlaced cameras use 0.
Flag_EquSerr=0 ; 0 = No Equalization and Serration
During vertical blanking without serration, there are no horizontal timing marks. Setting this entry to 1 causes Equalization and Serration Pulses to be generated on the composite sync signal.
Eq_Start=0x0 ; Line number where equalization begins
This defines the starting line of equalization pulses.
Eq_End=0x0 ; Line number where equalization ends
This defines the ending line of equalization pulses.
Tim_Gen_Clock_D4=0 ; For Line Scan Camera Only
Normally, the pixel clock from the PLL defines the fundamental frequency within the MV-1000 and is used as the basis of the Timing Generator signals. When Tim_Gen_Clock_D4=1, the PLL pixel clock will still be the fundamental frequency of the MV-1000 and MV-1100, but will be divided by 4 prior to entering the Timing Generator. While the register holding the value of Camera_Pixel_Per_Line is only 12 bits to count up to 4095, setting Tim_Gen_Clock_D4=1 allows line lengths close to 16K pixels.
Drive_Through_Module=0
This entry is used when an analog video is sent to the MV-1000 and digital control signals are sent to the camera from the MV-1100.
[Digital Camera Control]
This section is only used for the MV-1100 digital camera interface module.
Flag_DCI_Integration=0 ; 0 = No camera integration.
; 1 = Enable camera integration.
This entry turns on the EN INTEG signal on the MV-1100.
Flag_DCI_Double_Pulse=0 ; 0 = Single pulse for reset.
; 1 = Generate double pulse for reset.
Certain cameras use the distance between two reset pulses to control exposure. This parameter enables this mode.
Camera_Working_Mode=0x2 ; MC0 = OFF, MC1 = ON
This entry defines the Binary code from 0 to 7 that will be applied to the 3 static TTL control lines, MC0, MC1 and MC2. MC0 is represented by the 1 bit; MC1 by the 2 bit and MC2 by the 4 bit.
Counter_Clock_Source=0 ; Down counter clock source select:
; 0 = Line data valid
; 1 = Invert Line data valid
; 2 = Horizontal drive
; 3 = Vertical drive
The MV-1100 provides a counter that may be used to control the duration of certain control signals such as EXSYNC, VINIT, FRST or INTEG. The MV-1100 counter circuit counts down for each occurrence of whichever signal is selected by Counter_Clock_Source. Depending on the value of Counter_Ext_Trig_En described below; the count begins upon receipt of either a software trigger or the EXT_TRIG signal.
Counter_Value=0x10 ; Counter value: 0 - 0xFF
This loads the starting counter value.
Counter_Ext_Trig_En=0 ; 1 = External trigger signal
; 0 = Software trigger
This controls whether an external TTL pulse will begin the counting (1) or if a software instruction will be issued from the application program (0).
Counter_Ext_Trig_Pola=0 ; 0 = Falling edge of external trigger
; 1 = Rising edge
If an external trigger has been selected by the previous parameter, this selects the edge used for starting the counter.
Flag_LS_Exp_En=0
Certain cameras use an exposure reduction signal to reduce or control the exposure time. On the MV-1100 this is the PRIN signal. A 1 value in this parameter enables the PRIN signal.
LS_Exp_Start=0x0 ; For Line Scan Camera Only!
When PRIN is enabled, this defines the starting pulse position within the line in terms of the Timing Generator clock. This depends on the D4 settings in the [Timing Generator Control]. A value greater than or equal to 2 should be used.
LS_Exp_End=0x0 ; For Line Scan Camera Only!
When PRIN is enabled, this defines the ending pulse position within the line. This value should be greater than LS_Exp_Start.
Flag_LS_Exp_Polarity=0 ; 0 = Active low
; 1 = Active high
Under Version 2.1 and higher, this controls the polarity of the PRIN signal.
Flag_ExSync_Auto=1 ; 0 = Frame Rate control by EXSYNC signal
; 1 = Maximum Frame Rate
Some digital cameras which use the EXSYNC signal to control the line rate (and sometimes exposure) will run at the highest line rate when the EXSYNC signal is held HIGH. This parameter forces EXSYNC HIGH regardless of the previous Timing Generator control values for the EXSYNC timing.
[Digital Grab Control]
This section is only used for the MV-1100 digital camera interface module. It controls the polarity of input timing signals. It also controls how to deal with partial frames due to premature or asynchronous reset events.
Flag_LDV_Inv=0 ; 1 = Inversion of LDV passed to MV-1000
LDV (Line Data Valid) is the horizontal timing signal. Active low (falling edge) is the default and specified by 0 in this field. Active high (rising edge) is specified by 1.
Flag_FDV_Inv=1 ; 1 = Inversion of FDV passed to MV-1000
FDV (Frame Data Valid) is the vertical timing signal. Active low (falling edge) is the default and specified by 0 in this field. Active high (rising edge) is specified by 1.
Flag_PCLK_Inv=1 ; 1 = Inversion of P. CLK passed to MV-1000
PCLK (Pixel clock) is the pixel timing signal. Rising edge is the default and specified by 0 in this field. Falling edge is specified by 1.
Flag_Partial_Frame_Rmv=0 ; 1 = Remove partial frame on Async reset
Asynchronous reset may occur at any time and terminate the transfer of a frame prior to completion. When this field is set to 1, if a frame has not been completed when the FDV occurs it is discarded. When this field is set to 0, the partial frame will be transferred to the host and the lines, which were not captured, will be replaced by the last valid lines captured at that position.
[Color RGB]
This section is only used for the MV-1300 RGB input module.
RGB_Clamp_Control=0 ; 0 = Back Porch, 1 = Sync Tip
This field controls where the clamp voltage will be sampled.
RGB_Channel=0 ; 0 or 1
This field controls which of the two MV-1300 RGB channels will be used.
RGB_External_CSync=1 ; 0 = Separate H+V sync
; 1 = Separate C.Sync
The default (0) assumes separate horizontal and vertical syncs. If a composite sync is provided, this must be 1. When using Sync_On_Green, this must also be 1. (Note, the composite sync must be an active low signal.)
RGB_HSync_Polarity=0 ; 0 = active low, 1 = active high
This field controls the polarity of the horizontal sync.
RGB_VSync_Polarity=0
This field controls the polarity of the vertical sync.
RGB_Sync_On_Green=1 ; 1 = Sync On Green or Mono. C. Video
When composite sync is carried on the green video, this field must be set to 1.
RGB_R_Top=0x98 ; top level of Red channel A/D
This field controls the voltage of an 8-bit D/A converter used to specify the full-scale voltage of the incoming video signal. This value can range between 0 and 255. As the value decreases, any video signal above this threshold voltage is clamped at full-scale saturation. However, lower signal levels have finer effective resolution.
RGB_R_Bottom=0 ; bottom level of Red channel A/D
This field controls the voltage of an 8-bit D/A converter used to specify the low level (zero), offset voltage of the incoming video signal. This value can range between and 255. As the value increases, any video signal below this threshold voltage is clamped at zero. However, higher signal levels have finer effective resolution.
RGB_G_Top=0x98 ; top level of Green channel A/D
RGB_G_Bottom=0 ; bottom level of Green channel A/D
RGB_B_Top=0x98 ; top level of Blue channel A/D
RGB_B_Bottom=0 ; bottom level of Blue channel A/D
These controls work the same as the Red channel controls described above.
[Color C/S Video]
This section is only used for the MV-1350 composite video module.
CS_Channel=0 ; select 0-3 for R, G, B and S-V
When using the MVC-5-YC cable, the Red channel is selected with 0, Green with 1 and Blue with 2. S-Video is channel 3.
CS_AGC_Off=1 ; set to 1 to turn OFF the AGC
Normally, the Philips 7110 video digitizer chip has Automatic Gain Control turned ON. A 1 value in this entry turns the AGC OFF.
CS_Saturation=64 ; use the range: 0 - 127
This entry adjusts the saturation.
CS_Hue=0 ; use the range: -128 - 127
This entry adjusts the hue. This is a signed value. The default value is 0.
CS_Gain=0 ; when AGC is OFF, set(dB): -3, 0, 3, 6, 9
When AGC is OFF, this entry controls the gain in steps of 3dB between -3 and 9.
CS_Flag_PAL=1 ; for PAL, must set to 1
The default video into the MV-1350 is NTSC color. This flag switches to PAL standard timing.
CS_VCR_Mode=0 ; set to 1 for grabbing from VCR
VCR video signals vary more than camera based video signals. Setting this entry to 1 causes the PLL to be "looser", so the captured video is less "jumpy".
[Cables and Jumpers]
This section is used for documentation only. All entries in this section are ignored by the software.
Flag_White_Cable=0 ; Don't Care
The WHITE wire on the MVC-7 may be used for video input.
Flag_MiniBNC_Cable=0 ; Don't Care
On special MV-1000 boards, there is a special miniBNC connector.
Flag_Video_AC_Couple=1 ; Don't Care
If the video is AC coupled, the DC offset may not be used. When DC coupling is used, the Bandwidth filter and boost circuits are bypassed.
Flag_Sync_DC_Couple=1 ; Don't Care
Used when the sync is DC coupled.
Flag_Sync_Termination=0 ; Don't Care
Used when the sync is terminated.